/*
 *  Project:            timelyRV_v1.x -- a RISCV-32IMC SoC.
 *  Module name:        global_head.
 *  Description:        head file of timelyRV_SoC_hardware.
 *  Last updated date:  2022.07.22.
 *
 *  Communicate with Junnan Li <lijunnan@nudt.edu.cn>.
 *  Copyright (C) 2021-2022 NUDT.
 *
 */

  `define HW_VERSION      32'h1_4_5
  `define SINGLE_CORE
  
  
    //======================= peri_defination   ====================//
    //* peri &peri_id defination;
    `define NUM_PERI      4   //* = NUM_PERI_IN + NUM_PERI_OUT
    `define NUM_PERI_IN   3   //* inside  (UART, CSR, CAN;)
    `define NUM_PERI_OUT  1   //* outside (DMA;)
    `define UART          0   //* Address 1001xxxx is always for UART;
    `define CSR           1   //* Address 1004xxxx is always for CSR;
    `define CAN           2   //* Address 1009xxxx is always for CAN;
    `define DMA           3   //* Address 1007xxxx is always for DMA;
    //* id in peri_out, i.e., Peris in Pkt_Proc.v or MultiCore.v
    `define DMA_OUT       0
	  `define DRA_OUT       0
    //* irq_defination; 
    `define TIME_IRQ      3   //* time irq id, TODO: should before peri
                              //*   to have a higher priority;
    //==============================================================//

    //======================= number of PEs          ===============//
    `define NUM_PE        1   //* common PEs;
    `define NUM_PE_T      1   //* total PEs;
    //==============================================================//


  //======================= instr/data memory size ===============//
  //* instr/data memory size
    `define BIT_CONF      14
  //==============================================================//


  //* Using Xilinx's FIFO/SRAM IP cores
  `define XILINX_FIFO_RAM

  //* Using CUSTOMIZED_MUL logic
  // `define CUSTOMIZED_MUL

  //* time-relate info.
  `define NS_PER_CLK      32'd20

  //* open display function for UART
  `define OPEN_DISPLAY
  


  
